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Technology Stocks : Intel Corporation (INTC)
INTC 36.82+1.5%Dec 19 9:30 AM EST
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To: maui_dude who wrote (146657)11/1/2001 11:59:33 PM
From: Elmer  Read Replies (1) of 186894
 
Do you mean DFT (design for testability) ? If so, I think you are refering to scan cells, right ? Anything more than 5% area hit due to scan cells sounds a little too much to me and I am not sure why they couldn't remove/minimise it during the steppings.

Yes I meant DFT and 5% just isn't realistic. It's more like 10-15% depending on the style implemented. Don't know exactly about P4 but Intel tends to use muxed flops.

EP
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