SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Intel Corporation (INTC)
INTC 36.15-0.6%Dec 24 12:59 PM EST

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Noel who wrote (146679)11/2/2001 3:53:28 PM
From: Elmer  Read Replies (1) of 186894
 
Most designs are metal limited not transistor limited

I'm not so sure this is true anymore with 6 & 7 metal layers. Plus large SRAM caches don't have the routing issues random logic would.

Also, you will see a 25% cost gain from the transition to 0.13 micron as the P4 die size shrinks. But this comes from shrinking the design itself. Not due to a larger wafer.

Don't you mean cost reduction?

Going from .18u aluminum to .13u copper will not be a shrink but a compaction, meaning a complete relayout.

EP
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext