Intel Corporation (INTC) Message Board

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Intel Corporation (INTC)

INTC 41.99

+3.6%

1:04 PM EST

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next

To: Charles Gryba who wrote (147811)	11/13/2001 4:43:01 PM
From: wanna_bmw	Read Replies (1) of 186894

Constantine, Re: "The athlon was not supposed to be SMP either. The truth is that all the socket a athlon/durons do SMP out of the box." I was referring to the buzz about "glueless" SMP that is being tossed around the EV7 and Hammer platforms. In a "glueless" setup, the chipset logic is trivial, and most of the SMP logic is done on the side of the CPU. AMD even calls their new Northbridges "tunnels", since the memory controller is now absent. However, now that AMD is aiming Clawhammer for servers one quarter later than the desktop version, that tells me either that AMD has slipped their supposedly "simple" chipset designs, or that they have more bugs than they realized in the cache coherency logic of the CPU. Either way, it's just more bad news for them. wanna_bmw

Report TOU Violation

Share This Post

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next