Paul, Re: "From the technical disclosure of Hamster, the only major improvement I saw was the on-board memory controller - for reduced latency. I could detect no other significant architectural enhanceents."
While I respect a lot of the design teams over at AMD, I still don't believe that the company as an entity will be able to once again make a product and get it to market in time to be as great as the Athlon. Hammer is one of those things that sounds great on powerpoint slides, but may have a tough time getting off the ground.
Therefore, I only bring this up in an academic sense, just in the unlikely event that AMD hits the ground running with this.
You ask about micro-architectural improvements. Two things that are much improved over the K7 are the Branch Predictor Unit and the Translational Look-aside Buffer. From what I could gather, these improvements should help AMD in getting better scores with transactional processing tests, such as TCP.
Then there is also the integrated memory controller, which you mention, but don't forget the high speed Hypertransport links, which should give the CPU a lot more bandwidth to I/O.
I don't know what frequency advantages Hammer will have, but it does include a lengthening of the Athlon pipeline from 10-stages to 12. This might give the chip an advantage over the K7 in terms of potential frequency. Add that to the possible micro-architectural advantages, and I can see why they may feel justified in calling the first product Model 3400.
So I was just looking for your opinion, since you seem to know a thing or two about these kinds of things. Assuming that AMD can get the product out by the end of next year, do you think it can hit their aggressive targets for performance?
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