"PLEASE, can someone in the know put more light into this???"
What could be possibly unclear?
By definition, the leakage current is a parasitic feature
of a FET, the residual current when a transistor is not
swithching. In normal FETs this current was negligibly
small, but in sub-sub-micron transistors this is not achievable.
Therefore, by definition, you measure
the quality of FET under normal operating conditions
by measuring the overall current when the clock is stopped.
In old-technology CMOS microprocessors that usually
resulted in very significant power savings.
In Intel's recent technologies, the leakage current
has happened to be horrendously high, there were no
more power savings from just stopping the clock, so
they had to invent something to deal around that.
It turned out that after you stop the clock, the CPU
has an ability to retain internal logical states even
if you reduce the main voltage to certain level.
However, the CPU cannot operate at that "sleep"
voltage anymore if the clock is re-applied. To wake the CPU up
you need to rise Vcc back to normal level, and then
turn on the clock, so the CPU can proceed from the retained
sleep state. Therefore, the sleep voltage is not how
the leakage is formally defined, and cannot serve as
a meaningful transistor characteristics because it is
arbitrary.
Of course, if you want to characterize the possible
power savings for P-III, the 1.7A@0.85V is the correct
answer. However, the main point was to find out how
much of headroom has left in the current Intel technology,
and the way to measure it must be straightforward -
under the nominal operating conditions, apples-to-apples.
With 50% leakage at 1.13GHz on P-III, there are not
much left, IMHO.
Hope this helps,
- Ali |
