All, here is my humble try to analyze the P4-0.13 power consumption trend. The main assumption is that if certain changes
in <Icc> vs <frequency> occur when a design is moved
to new process technology, similar (proportional)
changes to basic functional elements of that dependence
will occur
on other CPU design that undergoes the same
technological transition.
1. Base point: P-III-0.18u Cpuid=68A, 24526408.pdf.
The trend is linear. Extrapolation of Icc data
to 0Hz = leakage = 2.1A
(Comment: extremely good process).
2. New process, P-III-0.13u, cpuid=6B1, 24976501.pdf
Data: extrapolation from two available data points,
1200 (20.6A) and 1133 (20.1A) gives the leakage of
11.65A, which differs from 9.5A listed in the specs.
Given benefit of doubt and possible inaccuracy at
full-scale current measurement, assume that
the published leak of 9.5A is correct.
Analysis of P-III transition to new technology:
1. The slope of <Icc> vs <frequency> line is
a measure of how effective the design is when
transistors switch. Due to new process, improvement
in switching portion is about 2x, or 1.93 times less
switching power.
(Comment: it looks like the fully expected improvement
from transistor shrink and lower RC interconnect delays).
2. However, the leakage has increased by a factor
of 4.5, (=9.5A/2.1A).
3. The baseline for 0.18u P4 is derived from Icc
given in 24919804.pdf, Table 5.
Extrapolation to 0Hz gives a leakage of 5.88A,
(Comment: very good compared to total 52A@1800.)
4. Now, applying the factors derived from p-III process transition,
a) slope decreases by factor 1.93
b) intercept(leakage) increases by 4.5, x5.88=32.5A.
Result: The P4 Icc at 2000 MHz is expected to be around 59A,
and at 2400 is around 65A, with leakage of 32A.
Now it may be more clear why recent Intel roadmap
for P4 is so conservative and does not go beyond
2.4GHz in 2002.
- Ali |
