Joey and Intel Investors - Looks like Intel's 0.13 micron process uses 248 nM lithography - and the AMDroid blokes that claimed the 193 nM stepper delays would delay their process ramp were WRONG - AGAIN !
Here's the abstract for Intel's IEDM presentation next month describing their 200 MM and 300 MM processes for 0.13 micron Copper processes.
his.com
11:10 a.m.
11.6 An Enhanced 130nm Generation Logic Technology Featuring 60nm Transistors Optimized for High Performance and Low Power at 0.7 - 1.4V,
S. Thompson, M. Alavi, R. Bigwood, T. Bramblett, J. Brandenburg, B. Crew, M. Hussein, P. Jacob, C. Kenyon, C. Lo, B. Mcintyre, Z. Ma, P. Moon, P. Nguyen, L. Rumaner, R. Schweinfurth, S. Sivakumar, M. Stettler, B. Tufts, S. Tyagi, J. Xu, S. Yang and M. Bohr, Intel Corporation
A leading edge 130nm technology with 6 layers of Cu interconnects and 1.3V operation has previously been presented[1]. In this work we enhanced the previous technology by further transistor improve-ments to support a 60nm gate dimension, 6-T SRAM device matching to allow low power and high performance operation at 0.7 to 1.4V, and a 5% linear shrink to reduce the 6-T SRAM cell to 2.00mm2 while still using 248nm lithography.
Saturation drive currents of 1.29mA/mm for N-ch and 0.65mA/mm for P-ch low VT device are the highest reported to date. These results have been achieved on both 200 and 300mm wafers. |
