Intel has new process technologies in development that compete with SOI - but have no drawbacks with floating substrate issues !
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9:05 a.m.
29.1 A 50nm Depleted-Substrate CMOS Transistor (DST),
R. Chau, J. Kavalieros, B. Roberds, A. Murthy, B. Doyle, D. Barlage, M. Doczy and R. Arghavani, Intel Corporation, Hillsboro, OR
In this paper we show a 50nm depleted-substrate CMOS transistor (DST) technology fabricated on thin-silicon body (<30nm) which demonstrates significant performance gain (subthreshold slopes<70mV/decade, DIBL<50mV/V, 30% Ion gain) and >30% power reduction over bulk Si CMOS without the floating body effect. |
