<Why is it that we never see AMD presenting "knock your socks off" presentations on process technology?>
9:55 a.m.
11.3 A High Performance 0.13 µm SOI CMOS Technology with a 70 nm Silicon Film and with a Second Generation Low-k Cu BEOL, J.W. Sleight, P.R. Varekamp, N. Lustig, J. Adkisson*, A. Allen*, O. Bula*, T. Chou, W. Chu, A. Gabor, P. Jamison, M. Khare, L. Lai, J. Ellis-Monaghan*, K. Peterson*, S. Rauch, S. Shukla, P. Smeys, T.-C. Su, J. Quinlan*, A. Vayshenker, B. Ward*, S.Womack, E. Barth, G. Biery, R. Ferguson, R. Goldblatt, E. Leobandung, J. Welser, I. Yang and P. Agnello, IBM Semiconductor Research and Development Center, Hopewell Junction, NY and *IBM Microelectronics, Essex Junction, VT
A second generation 1.2V high performance 0.13um SOI technology with a 70nm silicon film is described. This technology has the densest 6T SRAM reported to date with a cell area of 1.80um2. The advanced BEOL process includes 8 levels of Cu wiring with low-k interlevel dielectrics and SiC barrier layers.
10:20 a.m.
11.4 A High Density 0.10µm CMOS Technology Using Low K Dielectric and Copper Interconnect, S. Parihar, M. Angyal, G. Yeap, B. Boeck , D. Reber, A.Singhal, T. Van Gompel. B. Wilson, M. Wright*, K. Strozewski, D. Smith, T. Sparks, T. Stephens, F. Huang, R. Mora, L. Vishnubhotla, Y. Solomentsev, V. Arunachalam, A. Phillips, K. Junker, N. Ramani, M. Rendon, J. Molloy, K. McGuffin, A. Michel, R. Pena, D. Rose, J. Schmidt, M. Smith, M. Wilson, L. Terpolilli, P. Grudowski, Y. Jeon, J. Chen, P. Le, J. Sun, M. Hall, M. Woo and C. Lage, Motorola, Inc., Austin, TX and *Advanced Micro Devices, Austin, TX
In this work components of the next generation 0.10 um CMOS technology are presented. Dual and triple gate oxide options along with up to 9 levels of metal with low-k (keff ~3) dielectric and Cu metallization enable both performance and low leakage requirements to be met. |
