Semiconeng, this is very shocking.
"We believe that traditional SOI wafers cost many times more than bulk silicon--sometimes five to six times the cost," he said. "We've also had low-junction capacitance in our processors. So, SOI would not help us out very much."
Officials from Intel claimed that "thin SOI" or fully-depleted SOI has several advantages over competitive technologies. The "thin" SOI wafers prevent leakages through the chip substrate, lower junction capacitance, and reduce overall voltages in chips, the company claims.
It's becoming very clear now why Intel has skipped the first generation of SOI. With the expense and lower yields, it makes much more sense to wait until the second generation "thin SOI".
Very impressive.
Also,
In the future, Intel plans to "raise" or "thicken" the source and drain on the conventional transistor, thereby reducing resistance by 30% and increasing the mobility of electrons in the device.
In doing so, Intel, for the first time, plans to use epitaxial wafers. Epi wafers makes use of a modified planar process that deposits an oriented layer of lightly doped silicon over the silicon substrate.
In the TeraHertz transistor, Intel hopes to replace silicon dioxide with a new material with a "high k" value, reportedly In the 15-25 range. Current silicon dioxide has a value of 3.9 or so. The new high-k material also promises to lower gate leakage by 10,000 times over current silicon dioxide methods.
It looks like Intel is working on some very advanced techniques. This will no doubt allow them to more easily achieve terahertz switching speeds on their transistors, while other manufacturers are stumbling. When it comes to reaching 10GHz chips in 4-5 years and 20GHz chips after that, it's nice to know that Intel already has a head start, and that power concerns are already being considered, researched, and solved.
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