Ali, <font color=blue>IBM on Intel's SOI process.
Also note Intel's admissions.
Intel Corp. now will spin its own version, saying it will address circuit designers' gripes with SOI while retaining the technology's low-power, low-capacitance attributes. At the same time, the company has chosen a high-k gate dielectric to replace silicon dioxide, which many experts believe will become too thin to be effective below the 0.10-micron node.
Intel's decision to use silicon-on-insulator technology comes after five years of study and is considered a key step in reducing transistor leakage and voltages. By implementing its own brand of SOI with high-k gate dielectrics, the company claims it will be able to build transistors that operate at terahertz speeds within the decade, while keeping power consumption in check.
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But IBM fellow Ghavam Shahidi said the history effect has been overblown. "The history effect is less [of an issue] for fully depleted SOI, but it is a very small effect to begin with, and it's hard to measure. I'm not sure why Intel is making it a big deal," he said.
In fact, fully depleted SOI is not necessarily immune from floating-body effects, Shahidi contended. "If the source and drain are high, the body will charge up; that's a condition you see even in fully depleted [SOI]," he said.
Moreover, fully depleted SOI worsens short-channel effects, making it hard to attain multiple threshold voltages. And analog circuits still need to make contact with the body, which can't be done with fully depleted designs.
I think this shows [Intel's] lack of experience," Shahidi said.
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But the jury is still out on high-k dielectrics. Among the questions is the material's ability to withstand high temperatures when the source and drain regions are being doped.
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