Great collection of SOI statements from Intel posted at Ace's Hardware:
It sure looks like Intel has hit a wall at least as big as the one they smacked into with Rambus. Their research and development over the past 2 years has clearly been driving towards a non-SOI solution that turned out to not be feasible. They are having to start over from scratch, developing new process technologies they won't be able to implement until .09 or even .065 (2 to 4 years away). And they swore that they had proven in their labs that SOI provided little or no benefit at .09 and below. Meanwhile AMD licensed a working SOI process and has been perfecting it for over a year.
I did a Google search to find older articles aboout intel and SOI, since that seems to be the main topic of discussion right now ....
First of all intel's presentation on the topic of PD-SOI (partially depleted), and which started all that debate:
intel.com
Maybe it should be noted that this paper concentrates solely on performance, compare that to the recent publication which talks about power consumption and leakage (for some reason :-) leakage is the topic of the day anyway).
Then there is eetimes.com :
The intel guy (Mark Bohr) again says that SOI is of little use because junction capacitance (one of SOI's strength, for those who don't know) is not going to be a problem in the future, but that power consumption will. But instead of saying that SOI "might" be a solution for that problem too, he talks about chip design to solve it. In retrospects, it sounds like: "It's no good, unless we also have it".
Or eetimes.com :
(..) Other chip makers, most visibly IBM Microelectronics, have argued that performance gains from CMOS scaling are slowing, which will require a shift to silicon on insulator (SOI), to strained silicon, or perhaps to double-gated device structures. ButIntel has publicly rejected those approaches and said they will be unnecessary for the foreseeable future.
"Planar CMOS will be the standard, but within that basic structure will be a lot of materials changes that are really very exciting," Chau said. "We have many research projects into alternatives, but when it comes to manufacturing chips with one or two billion transistors - making those chips in an economical way in a volume manufacturing process - then planar CMOS will continue at least through the end of this decade."
So I guess, it is a planar CMOS process :).
And then there is a sentence in the official press release (http://www.intel.com/pressroom/archive/releases/20011126tech.htm?iid=update+011126b&) about that technology that made me laugh: The technology development is an important milestone in the effort to (..) remove the technical barriers that Intel and the semiconductor industry have only recently begun to identify. . That should read: "... that intel has only recently begun to identify, and the rest of the semiconductor industry already knew a year ago", no?
There are some other references where intel was publically dissing SOI, but that's nothing that people can't search for themselves ... also no such interesting statements to comment on ..
Anyway, none of the intel statements really work out the difference between PD-SOI and FD-SOI, so they usually just use the term SOI. And that's why the announcement seems to appear just out of nowhere ...
aceshardware.com
By Reinhard on Monday, November 26, 2001 12:44 PM EST |
