<I understand the problem you're having here Albert... >
I understand the problem you are having here Finger... The biggest problem is that you have no clue. From a 2-year-old IBM white paper on SOI:
www-3.ibm.com
"One solution to the bipolar transistor dilemma that has been under strong consideration over the last two-to-three years was to use very thin layer SOI films (less than 0.1 micron) called fully-depleted films."
eet.com
"But IBM fellow Ghavam Shahidi said the history effect has been overblown. "The history effect is less [of an issue] for fully depleted SOI, but it is a very small effect to begin with, and it's hard to measure. I'm not sure why Intel is making it a big deal," he said.
In fact, fully depleted SOI is not necessarily immune from floating-body effects, Shahidi contended. "If the source and drain are high, the body will charge up; that's a condition you see even in fully depleted [SOI]," he said.
Moreover, fully depleted SOI worsens short-channel effects, making it hard to attain multiple threshold voltages. And analog circuits still need to make contact with the body, which can't be done with fully depleted designs.
I think this shows [Intel's] lack of experience," Shahidi said."
So your first argument that fully depleted SOI is something new is bogus. IBM, AMD and others have been looking at thin-film SOI for years.
Your second argument about the uniqueness of high-k gate is equally bogus. From the same article:
"Intel's decision to adopt high-k dielectric material for insertion beneath the transistor gate isn't surprising, since most IC manufacturers are moving in the same direction. High-k dielectric films promise to let chip makers grow a thicker insulation layer to reduce leakage while keeping capacitance constant."
As a matter of fact, AMD has high-k SOI on their 90nm node roadmap.
While IBM, AMD and other have been quietly researching these technologies for years, Intel woke up some day and pulled an overnighter wiz-bang slide picture show.
Kap |
