Ali, Re: ""I'm guessing the area of the chip that runs at 1GHz is about as small as the area that runs at 4GHz."
Your guess is clearly wrong. Even the bus interface area
chip-architect.com
is at least 10% of P4 die."
Sorry to throw some mud in your clear picture, but doesn't the bus interface logic run at 400MHz? Likewise, doesn't the bus interface logic of the Athlon run at 266MHz?
Re: ""The cache issues traces every other clock, but that doesn't mean it's not doing work on every clock."
None of P4 caches can work faster than 1GHz, see
Message 16697144
The L2 cache is apparently 2x interleaved as it
follows form the die picture."
The L1 cache latency is 2-cycles, so you may be right. But, the L1 cache latency of the Athlon is 4-cycles, is it not? What difference does it make if the cache runs at half speed, if it still gets half the latency? Also, if you are right about the L2 cache being interleaved, then it will likely be run by the 2GHz clock with toggle flop for enable bit, not the 1GHz clock.
Re: ""Pentium 4 can reach higher clock frequencies for a small penalty in IPC"
IPC is total BS. The penalty from 2x longer pipe
is ranging from 0% on sequential codes, to 100%
on extreme-branching code, so it is a matter of
which code to pick for comparisons."
You seem to be avoiding the question. If what you say is correct, and a 2GHz Pentium 4 actually is predominately run at 1GHz, then how come it can beat a Pentium III at 1GHz by vast margins. You even admit that penalties for longer pipelines are larger. Shouldn't this decrease performance over Intel's previous architecture?
You can't have it both ways, you know.
Have fun,
- wbmw |
