Nice roadmap story as well:
siliconstrategies.com
Some high points:
The 2001 ITRS also warns that transistor-gate lengths in microprocessors could hit some fundamental process limits in just six years because manufacturers have greatly accelerated the physical scaling of those structures using post-lithographic process techniques (see Nov. 28 story).
Other surprises embedded in the new roadmap include the "deceleration" of several key technologies because they are proving to be more difficult to develop, said members of the ITRS committee during a press briefing on Wednesday. In particular, the 2001 technology roadmap pushes out milestones for progress in low-k dielectrics, metal cladding, and junction processes.
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During the press conference, Doering also revisited the concept of a "red brick wall" looming on the horizon--somewhere after 2005--due to major barriers in device shrinks and transistor scaling. In the 1999 roadmap, the industry was expected to hit the wall between 2005 and 2008. That is still the case, but the unsolved problems have shifted through what Doering said was a "porous" red brick wall.
"We can say it is essentially in the same place [between 2005 and 2007], but of course it is not 1999 any more," he said. "This is 2001. So, obviously we have moved closer to the red brick wall." Some improvements and solutions in lithography have been identified since 1999, but other areas of R&D have not gone as well as hoped, he added. "Parameters are moving in both directions," he said comparing technology solutions on one side of the red brick wall barrier.
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Within six-to-nine years, the cross-section of transistors will most likely look completely different than today's CMOS devices, said Chenming Hu, chief technology officer at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) and a member of the ITRS roadmap committee. He said the 2001 roadmap proposes three major groups of new transistor structures: ultra-thin body SOI (silicon-on-insulator) transistor; band-engineered transistor; and double-gate transistor.
The ultra-thin body SOI transistor will be fabricated in a very thin film of silicon, about 100 angstroms thick. This technique will enable researchers to build much smaller transistors without using special structures, according the ITRS officials.
The band-engineered transistor would introduce new or modified materials for CMOS devices so that electrons could move faster through the circuit. An example of this would be the use of germanium inside CMOS transistors. (Silicon germanium--SiGe--devices exist today, but they are mostly bipolar based and aimed at radio-frequency functions). The band-engineered device would also use mechanical stress in the structure to artificially control and improve the performance of transistors, explained the roadmap committee members.
A third leading candidate was called double-gate transistors. There are several approaches to this type of transistor, including "fin FET" and vertical transistor designs. These approaches essentially place one gate on top of the transistor and one on the bottom. This could be used to eventually reduce the gate lengths in transistors to as small as 9 nm, which is currently the target of the 22-nm node set for 2016. At 9 nm, these gates will only be made up of 30 silicon atoms, noted ITRS committee leaders.
Way neat stuff... |
