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To: kapkan4u who wrote (150448)11/29/2001 9:12:14 PM
From: Timothy Liu  Read Replies (1) of 186894
 
Allow me to point out one thing. The program you present effectively is a test of processor stall. It penalize a more super pipelined processor like P4. This has nothing to do with the speed of the decoder. P4 has about 20 pipe line stages compare to PIII (10-15?). So it has to spend almost twice as much cycles to fill in the pipeline after a stall.

The decoder frequency is irrelevant, even if the ID ran at 1/2 speed it must produce double output everytime otherwise it would not be a pipeline anymore.

My 0.02.
Tim
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