Dan: AMD will have a capacity of 5K * 13 * 315 = 20 million CPUs per quarter by the end of next year...
Uhmm… Do you seriously believe your own words?
First: Your 315 is high. Working backwards, your 315 die per wafer (good die, no less) corresponds to a die size of 85mm². And this is assuming a total yield of 100%. I know AMD quoted this number (315) in their material, but this is a theoretical max for Tbred only. In reality, there's not only a non-perfect yield, but also other (larger) dies being made.
Second: Your 5K is too high. This is an all-inclusive, theoretical maximum output. In reality, process development, test lots for new steppings, downtime due to equipment failure / malfunction, downtime due to process transition (SOI isn't going to just pop in there all by itself) etc. all lower that 5K by quite a bit.
Ok, so let's try a somewhat more realistic estimate (but still just a WAG):
5K wpw ideally, reduced to 4K wpw with line loss, process transitions, etc.
75% yield (probably too high for end of year, considering that SOI is being ramped)
300 die per wafer (probably too high, but let's go with it)
--> < 12M
And that's assuming every single processor is packaged perfectly and actually operates at a frequency high enough to sell.
Although certainly nothing more that a WAG, I'd say this is a very generous Wild *ss Guess…
-fyo |
