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Technology Stocks : Intel Corporation (INTC)
INTC 36.08-3.2%Dec 17 3:59 PM EST
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To: Charles Gryba who wrote (151149)12/5/2001 11:31:48 AM
From: kapkan4u  Read Replies (2) of 186894
 
This code needs to be improved to be conclusive. As it is written now, the PIII decoders can decode 3 instructions in 2 clocks. On the other hand the case sequence (load, add, store) has half the latency (or twice as fast per clock) on P4 than on P3.

The ideal code will force PIII and P4 to decode one instruction per clock. Also the case sequence should have the same latency on both chips.

Kap
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