Wanda, "This quote gave me the impression that Kapkan was comparing his program to real world code."
If the code does represent some real kernels,
how this coincidence may possibly change the original
intent of the program? It does not. So, do not
overblow your impressions and do not
attack "side effects" of the "Khapstone" benchmark.
"I have already refuted those findings with details that are neither tiny nor insignificant."
No you don't. No matter what your excuses are,
the fact remains that on a decode-limited application
the P4 running at "marketing frequency" of 2000MHz
has the same performance as P-III running at "true"
1000MHz. I just don't see how the internal details of
how many "decoders", 2 or 1.5, or else, can obscure
the simple conclusion: A decoder is a functional
unit, it is designed to deliver certain performance.
As the Khapstone benchmark shows, when decoders
are exposed to heavy decoding job,
2000MHz of p4 are equal to 1000MHz of P-III.
Therefore this points more and more to the conclusion
that majority of P4 die area is running at MarketHertz,
not MegaHertz. As I always have been saying, the Intel's
"MarketHertz" are no better nor worse than AMD's
"quanti-speed".
Plain and simple, is not it? End of discussion.
- Ali
"P.S. Still wondering where Intel accounts for stock repurchasing on their balance sheet?"
They are aside. What's your question?
Still wondering how TLB design affects task switching? |
