Tenchusatsu,
With the L2 cache, it's like RDRAM. The "speed" is judged by how fast the data transfers over the bus, not by its latency. For Pentium 4, data from the L2 cache is transferred at full speed. The latency is variable depending on clock speed, etc., but that's the way it's always been ever since the days of Pentium Pro.
You completely lost me. Either that, or nothing from what you posted makes any sense.
About data being transferred at full speed, meaning one bit of data per clock per line, I can agree with that. But it can be accomplished with what wbmw says.
But on latency of L2, it it is very relevant, because it determines how long the CPU is in the stalled state on L1 miss.
As far as latency of L2 being variable based on the clock speed, I don't think it is the case. Ever since L2 caches have been placed on CPU die, the latency is fixed in terms of processor cycles.
As for the trace cache, it can run at half speed because most of the transfers in and out of that cache are very sequential, not random like the L1 data cache. The trace cache can afford to run at half speed if it provided double the uops per transfer. Also, the trace cache needs to be relatively large (12K uops); however, larger caches are typically slower.
You mean larger caches such as L2, which is larger than Trace Cache?
Joe |
