Re: Dan3 is claiming that Intel will have yield crashes next year
You're being ridiculous, again.
You, Elmer, and Paul keep claiming Intel has some magic advantage in production, when the reality is both AMD and Intel have roughly similar capabilities.
Intel recently announced they would begin outsourcing chipset fabrication to UMC, while AMD is continuing to produce networking chips, embedded processors, and provide foundry services to Vantis and Legerity at its 1 1/2 FABs. So the percentage of FAB space used by AMD for CPUs may be higher than Intel, but AMD is not all CPUs, while Intel seems to be producing fewer non-CPU parts at its FABs. Intel also has 8 to 10 FABs dedicated to non-CPU production.
According to Mike Splinter of Intel, there were 5 .18 FABs available for P4 production in Q3 of 2000 (more than a year ago - slide 10) and intel was building FABs and upgrading older ones to provide 8 FABs for .13 productionn (slide 13).
intel.com
Intel is presently using 5 of its FABs to run P4, and 2 .13 FABs to run tualatin PIII/Celeron - total 7 FABs for CPUs. AMD is running 1 1/2 FABs, which means it takes Intel 4.5 times as many FABs to supply 3 times as many processors.
Intel has said it was going to use one of the 8 .13 FABs for flash, someday. That will leave 7 .13 FABs for CPUs.
AMD will only have to pay to equip and run one .13 FAB to supply 30% of the market, while Intel pays to equip and run 7 FABs to produce 2.5 times as many CPUs.
You are spewing this nonsense that Intel has yields significantly better than AMD's. It's just not true. The yields of both companies are probably similar (although the number of FABs Intel has to run is a bit disconcerting).
PS - here's a hint at how big some of Intel's FABs are, taken from someone's resume:
While at Intel, I managed the day shift for the Westech CMP area at Fab 11 New Mexico. Fab 11 processes 8 inch silicon with .35m , .25m , and soon .18m technology. The Westech polisher processes at the STI, poly, and oxide 1,2,3 and 4 layers, incorporating OnTrak , NovaScan , and PRI Automation technology in the planarization steps.
The area consists of 72 (and growing...) Westech 372M polishers, 24 Ontrak Series 0 and Series 2 scrubbers, and 24 PRI robots. Common challenges faced with such a large functional area included safety concerns, rapidly changing processing recipes and quality SOPs, unscheduled downtime, and cross training and proficiency issues.
I'm proud to say that the planar team successfully met production ramp-ups from 8500 wafer starts per week to over 13,000 wspw while lowering staffing from ~65 to 42 technicians.
mit.edu |
