Without devulging any inside knowledge on the subject you may be privvy to, what do you believe the difference in yield between AMD and Intel is? (ratio or in terms of percentage points) I'm really quite curious ;-)
This is a complicated question to answer. Using a % number is meaningless unless you are comparing 2 die of the same size, which we aren't. What needs to be compared is their defect density and there's no industry standard way to express it. This further complicates matters because I don't think Dresden's low output can be expressed purely in terms of high defect density. AMD isn't that bad. Something else is wrong. Because yield is a term that reflects functional/total die, it doesn't factor in speed. Despite all the debate here and on the Intel thread, I find it hard to believe AMD has this bad a yield problem in the normal sense of the word. Still we are left with the undeniably low output of F30, compared to what would be expected from a normal fab with normal defect density and all speed distributions being saleable. 2 variables here at play. Defect density and speed. As I said, I find it really hard to believe AMD has that many defects so we need to turn our attention to the other variable, speed. What reason do we have to believe AMD has a speed problem? What would be the characteristic signs of a company with speed problems? What is a speed problem anyway? First, a speed problem is simply not enough fast parts to meet the demands of the market. At worst a speed problem can mean too many slow parts that simply can't be sold. These aren't "defective" parts that bring your yield down(in the classic sense) but they can certainly lower the number of parts sold. Intel had a speed problem when they were trying to push 1GHz CuMine parts last year. To address this Intel ran a special fab line using a non-standard process step. They got more fast parts but at the expense of lower yields and lots of nursing. It wasn't mainstream meaning that most CuMines were standard process, but it did supply enough units to allow Intel to have a pressence at 1GHz. Now look at AMD. Numerous reports keep cropping up about the high speed XPs using .13u transistors with channel lengths down to 70nm. This is extreme. In my opinion, this is the analog to Intel pulling every trick possible to produce enough 1GHz CuMines to appear to be competitive. This is why some of us say that AMD has already shot their .13u wad in a desperate attempt to "appear" competitive. If AMD has to use these extreme techniques to produce a small number of ~1600MHz parts, what does that say about their standard process which is used for the majority of their output? It says that there is a strong likleyhood that the normal distribution probably includes material too slow to sell.
So you have a special line using extreme lithography techinques slowing things down and a standard process that probably produces some material that is unsaleable. No need to introduce low yields in the classic sense. All this would go a long way to explain the low output from F30. All other attempts to explain the low output have really just been apologies contrived to make excusses for why AMD throttles it's moneymaker.
Tualatin is clearly an awesome low-end chip - especially if Intel can ramp it in frequency (and initial indications would seem to support this). The main barrier atm would appear to be the performance of the P4! If Intel drove Tualatin hard and coupled it with a higher FSB, P4 would be a deep trouble in terms of performance ;-).
This is a good argument when applying it to the Willamette version of P4. But P4 won't stay first generation. Intel needs to move the market to second generation P4s and if that means de-emphasizing an otherwise good product (Tualatin) then it's in Intel's best longterm interest. P4 will really hit it's stride on the 3rd generation. Isn't Athlon on the 3rd generation now with XP being 4th? How much better does XP look now compared to the first Athlon introduced with offdie L2? Should you limit your future expectations of P4 to what you can see today?
As it is, I believe Intel will keep Tualatin on a significantly slower bus than P4 and limit the ramp in frequency (e.g. by optimizing for high yield and low die-size instead), at least until P4 is well on its way on .13µm.
My guess is you're right.
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