Sun Divulges UltraSparc-IIIi Chip Plans
Computergram International
Date: January 9, 2002
Number: 4328
By Timothy Prickett Morgan
Sun Microsystems Inc has raised the curtain a little bit on the "Jalapeno" family of UltraSparc-IIIi processors that are due to begin shipping in workstations and entry servers somewhere in the middle of this year. The Jalapenos, which will be based on the most advanced chip making processes available from Sun's chip fab partner, Texas Instruments Inc, will follow in the UltraSparc tradition of using the i-Series of processors to push the design and fabrication limits of TI's processes and the clock speed of Sun's chips. Sun has recently taped-out the design and has chips coming off TI's fab lines running at speed in its labs.
The Jalapenos will, in fact, be the first chips manufactured using TI's 0.13 micron Epic7 seven layer copper process. Sun and TI have shrunk the UltraSparc-III core with the Jalapenos, integrated an L2 cache memory, and stripped out a lot of the electronics that are necessary for building large n-way servers so they can create fast, relatively inexpensive, and simple microprocessors that are suitable for Sun's workstations and high-density servers. In Sun's server line, the Jalapenos will be aimed specifically at the sweet spot of machines with from one to four processors.
Sun has long been expected to launch a four-way server codenamed "Cherrystone," which is essentially half of a current eight-way V880 "Daktari" server; the Daktaris were announced late last year, and the Cherrystones were originally supposed to precede them to market. Exactly when the Cherrystones will be launched is unclear, but they will be clearly aimed at competing against the large cache RISC-Unix server offerings of Hewlett Packard Co, Compaq Computer Corp, and IBM Corp, as well as a slew of server vendors who sell servers using Intel Corp's Pentium III Xeon, Pentium 4 Xeon, and Itanium servers. The Jalapenos seem aimed at ultra-dense products that currently use the Intel Pentium III small cache processors.
The Jalapeno chip will run at 1.3 volts using the 0.13 micron copper process from TI, and will have clock speeds that range from 1GHz to 1.4GHz. According to Sue Kunz, director of product marketing for Sun's processor products group, the initial launch speed is expected to be either 1GHz or 1.1GHz. Faster Jalapeno processors will be created by adding low-k dielectric to the copper process, much as IBM will eventually do with its Power family of RISC processors for Unix and OS/400 servers. TI is current using a 0.15 micron copper process to make the regular UltraSparc-III+ processors, which run at 900MHz today and which will clock at over 1GHz sometime in February. The earlier generations of UltraSparc processors did not use copper processes and ran 600MHz and 750MHz clock speeds. The Jalapeno chip will have a total of 87.5 million transistors, with 63 million of those transistors comprising the integrated 1MB of L2 cache memory.
With high density servers, the amount of processor power a chip has is sometimes secondary to the amount of electric power a chip consumes and the amount of heat the chip throws off. Kunz reckons that a Jalapeno chip running at 1GHz or 1.1GHz will throw off around 50 to 60 watts, and that even running at 1.4GHz, Sun and TI can keep the heat down to 70 to 80 watts by using low-k technologies. (Low-k could be available by the end of 2002 or early 2003). Contrast this with Intel's "McKinley" Itanium processors, which are expected to throw off 130 watts of heat. Kunz says that Sun has made comparisons across all the chips out there, looking at SPECint performance per watt and TPC-C throughput per watt, and that the Jalapenos will be as good as anything out there. "The limiter in this market is power. Period." She says that the Jalapenos will have a profile that is very similar to the 1.2GHz Athlon processors from AMD.
The Jalapeno chips will have the same 14-stage, non-stalling pipeline and six execution pipes as the regular UltraSparc-III processors. The two chips also have the same Level 1 64KB data and 32KB instruction caches, as well as tinier caches associated with prefetching and branch prediction. The chips both have two integer units, two floating point, one load/store, and one branch unit. Sun is targeting performance greater than 550 SPECint2000 with the Jalapeno chips running at their peak speed; with tweaks to the Forte 7.0 compilers, those SPECint2000 ratings could go up another 50 to 70 points.
There are some differences between the new UltraSparc-IIIi chip and the old UltraSparc-IIi chip used in Sun's entry server and workstation products today. The UltraSparc-IIi chips included interfaces to the PCI bus integrated on the chip; interfaces to SDRAM were external to the chip, as was the L2 cache. The Jalapeno chip integrates the L2 cache memory as well as interfaces to DDR1 SDRAM memory. (The "Cheetah" UltraSparc-III chips also include integrated SDRAM memory interfaces.) The Jalapeno chips will also support 4MB translation lookaside buffer (TLB) pages. The US-III and US-II chips have supported 8KB, 64KB and 512KB TLBs up until now.
The Jalapeno chip also includes interfaces to a new bus, called the JBus, which is a new interconnect bus for the chip that Sun has designed to replace traditional PCI and SMP electronics. "JBus will give good performance as long as you don't try to build something big out of it," says Kunz. Hence the Jalapeno server is aimed at servers with 1 to 4 processors only. In concept, the JBus system interconnect is very similar to AMD's HyperTransport interconnect, which is getting a lot of attention in the entry server world right now. But Kunz says that JBus is not based on HyperTransport.
The JBus design supports from one to four processors, with eight memory banks per processor, each supporting a total of 8GB of main memory. Peak memory bandwidth is estimated to be around 4.25GB/sec per processor.
The JBus design incorporates seven ports - four for processors, two for I/O and one for some mysterious use that Sun has not identified and which is probably intended for system clustering. The JBus is 16 bytes wide and runs at 200MHz. On the I/O bus portion of the JBus, Sun has been able to hit more than 500MB/sec of bandwidth both reading and writing on PCI peripherals, which plug into the I/O portion of the JBus.
The Jalapeno chip will be first used in the two-way "Enchilada" and four-way "Chalupa" entry level Solaris servers, which we have heard will be sold as the Sun Fire 240R and Sun Fire 440R. timpm@computerwire.com |
