Combjelly, Re: "So you are saying that they will go 6 months without being able to get the speed past 1.93GHz on bulk Si? Why do you believe that? That does not match up with what either company has been able to do... "
Actually, I think 1.93GHz is a reach goal for them at .13u bulk si. I think so because I believe that their transistor gate lengths are already as small as those found in an advanced .13u process, and aren't likely to shrink further when AMD shrinks the rest of the transistor. I think AMD's full .13u bulk si process will buy them marginal improvements - 1.73GHz and 1.8GHz will come easily, but 1.86GHz and 1.93GHz will be lower volume, or perhaps even impractical. I think AMD's current roadmap is based on the wishful thinking that they will have SOI available in Q3, which will probably give them 200-300MHz over the lifetime of the process. 2.2GHz for AMD would be about a Model 2800+, which is one speed grade greater than their roadmap shows for Barton, and this in my opinion will be the fastest K7 manufacturable at .13u SOI.
Hammer will probably gain 200-400MHz over its lifetime above Barton, and I also expect about 10-25% improvement in IPC right off the bat, mostly due to the integrated memory controller, but also due to the faster bus speed, extra cache, and minor micro-architectural improvements. At 2.2GHz and 20% bloat in model numbering, AMD could derive the M3400 (M2800 * 1.2) rating that they were predicting for the 4th quarter (but I think it will get pushed out until Q1'03. By the end of the first half, AMD may reach 2.6GHz, and similar 20% model number bloat, AMD could derive the M4000 rating (M3400 * 1.2). By the end of 2003, they think they will have another process shrink, which will allow them to reach 2.8GHz and M4400 (M3700 * 1.2). 100nm or 90nm manufacturing should allow greater than this in 2004, if they are successful ramping it up (which I think will be difficult only one year after starting the ramp for SOI). Also, I think a 20% bloat would be on the high end of actual achievable scores, and if this is what they are aiming for, they will find it hard to justify the performance. But then again, with AMD hiding the real megahertz more and more, no one may realize the difference.
However, it will obviously mean that they will have to live up to Pentium 4 performance to a greater degree. With those aggressive numbers, they are probably assuming that Intel plans ramping up megahertz a lot more, without improving IPC. I can't say I know for sure, but my guess is that this assumption will probably be wrong. Intel is bound to improve IPC through refining the core and fixing performance issues that come along. Whether it's enough to compete with the level of IPC in Hammer, I don't know. But that's my interpretation of AMD's roadmap, which I consider aggressive. AMD still has to execute to it in order for it to work, and if they happen to delay SOI, delay Hammer, delay 100nm conversion, or any of these aggressive speed grades along the way, it won't be possible.
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