I would have more to say but I doubt if there are many people here with advanced degrees in particle physics
Oddly enough, I have a Ph.D. in EE, specializing in device physics, and part of my current job involves estimating soft error (i.e. those pesky neutron and alpha particles previously mentioned). Can't imagine a topic ever straying so close to my occupation!
As far the Uncle Frank's question, the easy answer is that a disk stores the bits magnetically whereas Flash stores electronically. Neutron interactions result in charge generation, which can be collected by the floating gate (where Flash stores its own charge) to disrupt the stored bit. This doesn't happen in magnetic media (or at least to the same degree--never say never). The metal box is largely a non-issue--it will stop alphas, but neutrons pretty much pass right through (and, for the most part, they pass right through your head, the case, the silicon, and back out again without interacting with anything--it's pretty much all free space to them).
I would guess that Flash is pretty "strong" with regard to SER (soft-error rate) in that the ability to collect charge isn't all that large. When a neutron interacts with silicon, it generates a recoil ion that is literally displaced and generates charge along its post-strike path. For Flash, only the part of the path that goes through the (thin) gate can collect charge (because there is SiO2 on both sides {ONO on one side, for the purists}, which will effectively reduce the collection efficency). In short, I doubt flash devices are all THAT disturbed. I'd be more worried if my laptop were in sleep mode (where the state is stored in DRAM).
Also, if one is using flash for picture storage, an upset bit would probably never be noticed.
I'm a little curious about your claim that Intel ignores SER while IBM does not, based strictly on availability of ECC. IBM makes boxes, whereas Intel does not. Intel and other companies, however, do make chipsets that support ECC for Intel microprocessor, so any system maker could use those chipsets, thus making an Intel server that was just as robust as IBM (well, this is assuming DRAM upset it your only problem, but that was the implication in your mail--there are loads of other SER mitigation techniques that one or both companies probably does). If conference papers are any guide, Intel (et al, like MOT) takes SER seriously--in fact, Intel is "famous" for first showing SER from alpha particles in their packaging back in the days when they made their money in SRAM.
On the other hand, I would agree that "mainframe" transaction-based systems have taken SER seriously for longer than anyone (don't want that ATM transaction to have a bit switched), and IBM has been in that market since the get go.
Regards,
Steve |
