SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: TigerPaw who wrote (142138)1/25/2002 2:40:58 PM
From: combjelly  Read Replies (1) of 1582632
 
"I assume it will be closely compatible with X86 and not just emulated like the Itanium"

Yup. That is the beauty (and the ugliness) of the way AMD did it. The architecture of 64 bit mode is just a cleaned up version of 32 bit x86, just like 32 bit x86 was a cleaned up 16 bit x86. So the decoder for x86-64 decomposes the ops to the same uops as it does in 32 bit mode. As a result, only the decoder needs to be different. It's ugly because, well, x86 is ugly. In addition, some of the extended instructions need extra bytes to implement them. And that causes the decoder problems. But, on the upside, the register file is general purpose and there are a total of 16 SSE registers instead of 8. So code can be more well-behaved and it may not have to hit memory as often. And that is always a big plus.

Bottom line, 32 bit code runs about as fast as 64 bit code. There will be some differences, the above mentioned registers should make 64 bit code faster, but it has to move around 64 bit instead of 32 bit pointers and there are those extra bytes on some instructions. So YMMV, as always...
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext