SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 213.94-0.4%10:38 AM EST
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Tenchusatsu who wrote (68909)1/25/2002 7:53:07 PM
From: pgerassiRead Replies (1) of 275872
 
Dear Tench:

You seem to have difficulty realizing that the interconnect between Hammer CPUs is HT links directly between CPU packages. A single HT link attaches to the NB which becomes simply an AGP port and 2 HT links, one to the CPU and the other to the SB. A Clawhammer which has 2 HT links, one connects to the NB and through it to SB, PCI buses, etc. and the other connects to another Clawhammer. This interconnect link has no chips between the CPUs as the logic resides in the bridge inside each CPU. Thus Serverworks (and any other chipset vendor) only can design the NB/SB/PCI/etc chipsets off of one HT link in each CPU. A 2 HT link Clawhammer can thus be used to build 1 or 2 way SMPs with at most 1 hop latencies (chaining the CPUs could make for an N way SMP with a maximum latency of N-1 hops).

The Sledgehammer can go beyond this in two ways, dual cores could double the above way SMP systems and 3 HT links allow for a mesh of CPUs to be connected. That is how greater than 4 way systems could be built. Up to 4 nodes of dual cores could be built with at most, a 2 hop latency yielding an 8 way system. And each node (CPU chip) still has its own memory channels (1 or 2) and I/O link. Besides in writing device drivers, I had to contend with multiple PCI busses with sometimes 2 or 3 on a single I/O card alone. It is available now (even AMD has connected multiple PCI buses in its chipsets so they have the know how already).

Further Hammers could be extended by adding addition HT links. 4 HT links yield a 16 way system with a 3 hop latency. 5 HT links yield a 32 way system and so on. The real reason this works is the HT bridge in each CPU chip of the Hammer series. Now Serverworks could make such a bridge for connecting Clawhammers into a more than 2 way system but, it must be cheaper than simply using higher SMP capable CPUs else, who would want it? Another possibility is a HT connected memory controller to extend the amount of memory available to systems. There are many more such add-ons that would make sense to a core ccNUMA SMP system.

You seem to forget the techniques that have led us to today's highly complex CPUs. Black boxes (later ICs) being used to build systems block by block. Perhaps you have forgotten older connectivity system building blocks that have been tried before (like the old transputers making MMP systems easy to make).

Try to remember history before making such generalizations. Those that do are regularly forced to "eat crow".

Pete
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  

HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2025 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News