Rambus RaSer Cell Sets New Benchmark in Integrated Serial Link Technology; RaSer Cells Now Available in 0.13-micron CMOS Process
Story Filed: Tuesday, January 29, 2002 9:00 AM EST
LOS ALTOS, Calif., Jan 29, 2002 (BUSINESS WIRE) -- Rambus Inc., the leading provider of high bandwidth chip connection technology, today announced the availability of an extremely low power RaSer serial link cell in 0.13-micron process. The introduction sets new standards for operating range, low power and small size. Rambus will demonstrate this newest generation of RaSer(TM) serial link technology at DesignCon in Santa Clara, California.
Rambus has developed its second-generation family of cells based on serializer/deserializer ("SerDes") technology. The latest RaSer cells operate from 1 to 4 gigabits per second (Gbps), while consuming less than 100 mWatts of power at 2.5 Gbps and uses less than 0.5 mm squared of area in a 0.13-micron CMOS process.
"The small size and low power make the latest RaSer cells ideal for applications that integrate multiple links on one chip," said Kevin Donnelly, vice president of the Network Connections Division at Rambus Inc. "The RaSer cells are available in single-, dual- and quad-link configurations. For example, a 32-link serial link switch could be implemented in less than 6 mm by 6 mm and consume less than 5 watts."
Rambus will demonstrate the 0.13-micron 3.2Gbps RaSer quad serial link technology for the first time at DesignCon, January 29-30. As network equipment moves to support higher line rates and higher aggregate switch bandwidth, developers are integrating SerDes functions into line card and backplane traffic manager devices. Speed, reliability and low power are key to enabling these next generation line cards and switch fabrics. Rambus will demonstrate the low jitter, low bit error rates, and extremely low power of the new RaSer 0.13-micron 3.2Gbps quad SerDes cell.
RaSer(TM) Cell Technology
RaSer technology from Rambus offers designers a scalable serial link architecture that addresses current and future serial link applications requiring the highest bandwidth. RaSer technology can be employed across a variety of different networking applications, including WAN router and switch backplanes, Gigabit and 10-Gigabit Ethernet, InfiniBand(TM), Fibre Channel, and fiber optic network interfaces and any other custom chip-to-chip applications.
Rambus RaSer cells are offered as an analog core library cell, for ASIC and ASSP designs. A complete serial link solution, the RaSer cell contains serializer, transmitter, receiver, deserializer, and clock recovery circuitry. The cell is designed to meet the physical layer requirements for a wide range of serial link applications, each of which may have different logical requirements (protocol, framing, coding, etc.). As a replacement to stand-alone discrete serial link components, the RaSer cell may be integrated with other communications functions in order to offer higher value network services and reduced component count. |
