Toshiba cuts capacitor from DRAM cell design
By Yoshiko Hara
EE Times
(02/07/02 14:40 p.m. EST)
siliconstrategies.com
TOKYO — Toshiba Corp. has developed a one-transistor, no-capacitor cell structure that it claims solves the difficulties encountered in producing DRAMs in sub-0.1-micron process technology. The company presented the approach at the International Solid-State Circuits Conference in San Francisco this week.
A conventional DRAM cell consists of one transistor and one capacitor. But when a DRAM is processed at below 0.1 micron, this structure becomes a bottleneck. Even if the transistor shrinks, the capacitor has to maintain a certain capacity. In order to do so, the capacitor has to be formed deeper and deeper in a trench-cell structure, or stacked higher and higher in a stacked structure.
"To solve this bottleneck, new approaches have been proposed, but those approaches require new materials or complex cell structures," said Takashi Ohsawa, senior specialist of the advanced memory design group at Toshiba Memory Division. "The cell structure named floating-body cell that we've developed has a simple structure in the smallest size of 4F2, does not require new material and is scalable, though it is not nonvolatile," Ohsawa said.
The floating-body cell (FBC) is formed on a silicon-on-insulator (SOI) wafer and consists of one MOSFET, whose body is electrically floating. Making use of the floating body, a charge (holes for nMOS) is stored in and drawn out from the body, which functions like the capacitor in a conventional DRAM cell.
"To design circuitry on SOI, a new design was needed because of this floating body, which was a kind of barrier to shift SOI. On the contrary, the FBC makes use of the floating body. The FBC is quite a suitable cell structure for SoC [system-on-chip] on SOI," Ohsawa said. |
