IDT Introduces Industry's First Double Data Rate FIFO Family for High-performance Communications Applications
TeraSync(TM) DDR FIFOs Deliver Twice the Bandwidth and Highest Data Rates on the Market
SANTA CLARA, Calif.--(BUSINESS WIRE)--Feb. 18, 2002-- IDT (Integrated Device Technology, Inc.) (Nasdaq:IDTI - news), a leading communications IC provider, today introduced the high-performance TeraSync(TM) DDR FIFO family, the industry's only FIFO family with double data rate capabilities.
Designed to offer the next level of performance through a double data rate interface and advanced feature set, this family of devices offers clock cycle speeds up to 250 MHz and targets data rates up to 40 Gbps, more than doubling the bandwidth currently available for leading-edge applications in the enterprise and carrier-class markets. The TeraSync DDR FIFOs are optimized for SONET, Fibre Channel, and Gigabit Ethernet, as well as image processing and instrumentation applications.
Leveraging IDT's heritage and leadership in FIFO products, the TeraSync DDR FIFO family provides a cost-effective solution optimized for bandwidth-demanding applications, enabling customers to more efficiently manage data traffic. When using two TeraSync DDR FIFOs in parallel, this solution also provides the industry's most efficient means for applications to implement OC-768 line-rate buffering. By conserving input/output (I/O) pins and reducing the clock frequency by half, the devices achieve 500 Mbps bandwidth per pin and consume less board space than any other off-the-shelf solution. The devices offer an industry-leading density of up to 5 Mbits to better service ever-increasing amounts of data, voice and video traffic within high-bandwidth communication systems and hardware.
Through the decoupling of clocks and buses, the TeraSync DDR FIFO family enables high-speed and high-density data buffering to enhance overall system performance. The family also solves other traditional inter-chip communications problems such as rate matching and bus-width matching, and is offered in a unique set of x10, x20 and x40 configurations. The extra bits in these configurations provide byte and packet boundaries that allow the TeraSync DDR FIFO devices to denote valid bytes and perform packet delineation.
``With the TeraSync DDR FIFO family, IDT further demonstrates its position as a leader and innovator in the FIFO marketplace,'' said Mario Montana, IDT's director of FIFO products. ``We are offering a new mechanism to accommodate high-performance, leading-edge applications, providing the highest data rates available without any competition in terms of performance, density, board space or cost.''
Devices Streamline Data Traffic Management
In addition to its traditional FIFO functionality and double data rate capabilities, the TeraSync DDR FIFO family delivers extremely low power consumption and an advanced set of features. The devices offer double data rate to single data rate matching, which allows one port of the device to operate in double data rate mode, while the other port operates in single data rate mode. TeraSync DDR FIFOs also supply user-selectable I/Os, supporting 2.5-volt LVTTL/ LVCMOS with 3.3-volt tolerant inputs, 1.8-volt LVCMOS/eHSTL, and 1.5-volt HSTL. This user-programmable configuration is available on each port and enhances high-speed operation by providing the flexibility to interface with devices of various voltage operation levels.
IDT's TeraSync DDR FIFO devices also support source echo read clock and enables, as well as a re-transmit from mark function. The echo clock feature allows interfaces to run at speeds up to 250 MHz by controlling the phase and timing relationship of the output data and clock signals.
Designers may utilize the TeraSync DDR FIFO family's advanced BGA packaging, which enables increased system bandwidth without compromising board space. These 208-ball package options include a JTAG interface that facilitates debug and test capabilities for optimized manufacturing and board yields.
TeraSync DDR FIFOs Expand IDT's FIFO Leadership
As the market and volume production leader of all FIFO products, IDT offers more than 300 FIFO solutions to suit a broad range of applications. IDT continues to strengthen its leadership position in the FIFO market, both through ongoing product improvements and the introduction of innovative new products driven by customer design requirements, such as the TeraSync DDR FIFOs announced today and multi-queue FIFOs announced in September 2001. IDT was the first supplier to introduce innovative asynchronous, synchronous and specialty FIFO architectures and has since captured more than 65 percent of the FIFO market.
Price and Availability
The TeraSync DDR FIFOs are currently available in production quantities. Volume pricing starts at less than $38 in 10,000-unit quantities for commercial and industrial-temperature grade devices. Additional product information can be found on IDT's Web site at idt.com.
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IDT's TeraSync DDR FIFO Family
Pro- Pric-
duc- ing
tion (based
Part Max Freq/ Avail- on
Number Configuration Pin/Package Data Rate able 10K
quantities)
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72T4088 16Kx40 208-ball BGA 250 MHz/500 Mbps Now $37.74
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72T4098 32Kx40 208-ball BGA 250 MHz/500 Mbps Now $48.04
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72T40108 64Kx40 208-ball BGA 250 MHz/500 Mbps Now $60.04
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72T40118 128Kx40 208-ball BGA 250 MHz/500 Mbps Now $64.26
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72T2098 32Kx20/64Kx10 208-ball BGA 250 MHz/500 Mbps Now $37.74
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72T20108 64Kx20/128Kx10 208-ball BGA 250 MHz/500 Mbps Now $48.04
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72T20118 128Kx20/256Kx10 208-ball BGA 250 MHz/500 Mbps Now $60.04
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72T20128 256Kx20/512Kx10 208-ball BGA 250 MHz/500 Mbps Now $64.26
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About IDT
idt.com
TeraSync is a trademark of Integrated Device Technology, Inc.
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Contact:
IDT Corporate Communications
Lindsay Sakamoto, 408/492-8314
E-mail: lindsay.sakamoto@idt.com
or
KVO Public Relations
Kara Kraft, 503/221-2335
E-mail: kara_kraft@kvo.com |
