SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 231.83+1.7%Jan 16 9:30 AM EST

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: dale_laroy who wrote (71909)2/19/2002 1:27:23 AM
From: Joe NYCRead Replies (1) of 275872
 
dale,

Via started out their V-Link with 133 MB/s or 266 MB/s bandwidth, which was 1x. Thefuture implementations will be 2s, 4x and 8x of that

Take a look at this presentation: platformconference.com slide 16.

It looks like Via is planning to have a northbridge with:
- path to CPU (P4 bus, EV6, HT)
- AGP path (up to 8x)
- high speed (4x = 1 GB/s, 8x = 2GB/s) - I am not sure if this can coexist with AGP or it is either one or the other)
- path to southbridge
- path to memory DDR (1 or 2 channels)

Can you count all those pins? My god. Via wants to be the center of Universe. I have a feeling that they are biting a bit more than they can chew.

Joe
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext