Advanced Micro Devices - Moderated (AMD) Message Board

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD)

AMD 214.11

+3.9%

3:59 PM EST

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next

To: Ali Chen who wrote (72826)	3/3/2002 10:35:38 PM
From: THE WATSONYOUTH	Read Replies (2) of 275872

The 17A is specified in "deep sleep" state for both 2 and 2.2GHz NWs. Deep sleep means stopped clock with the same Vcc. Co-incidentally, linear extrapolation of dynamic currents at 2.2 and 2GHz gives exactly the same number - 17A. The exact budget for this leakage is not known. There are suspicions that certain semi-analog circuits that use multi-threshold transistors did not scale well after the shrink, so not only the classic off current is there. My position was that I do not know and do not care, but the fact does exist that 0.13um CPUs consumes a lot of static current even when clock is totally stopped. I'm trying to rationalize this "deep sleep" current based on a reasonable estimate of device off current and I'm afraid I can't even get close. Let's assume there are perhaps 25 million devices in L2 cache and perhaps 40 million in logic and L1 cache. (anyone have better estimates?) Lets also assume the cache devices average .4um in width and the logic devices average 4um in width. We know Intel is using both high and low Vt devices in P4 design (for the first time) Now ... from their 2001 IEDM paper, they specify 10nA/um off current for their L NOMINAL high Vt devices and 100nA/um off current for their L NOMINAL low Vt devices. But, what do they mean by NOMINAL? Not what you might think. Also in the paper is a NFET Vt roll off vs. L gate plot. If one looks at the low Vt plot at high drain bias, one sees a Vtsat of perhaps 140mv at 60nm L gate. At 50 nm L gate, the Vtsat drops rapidly to 50mv (1 data point) Thus, this 60 nm L gate which Intel calls NOMINAL must actually be a sort of a minimum L gate (mean) for proper operation of low Vt circuits since I can't believe they can live with 50 mv Vtsat. In fact, Intel defines Lmin = L NOMINAL - CD control. I believe this CD control to be the actual maximum across chip linewidth variation (ACLV) This ACLV therefore must be in the order of +/- 10nm 3 sigma. I doubt very much that they actually achieve that since the masks are typically not even that good. But this 2.2GHz part can't be anywhere near L NOMINAL = 60nm because they claim they will reach 3GHz with this technology. So .... where is it in relation to L gate = L nominal which I believe is actually the minimum L mean for this technology. I would guess that this 2.2GHz part represents an L gate of perhaps 85nm which will decrease to 60nm = L NOMINAL = Lmin + CD control at approx. 3GHz. But at 85nm mean, there should be very few gates below 75nm which means even the low Vt devices should have off currents well below the 100nA/um specced at 60 nm. I can only get up to near 17A if all devices are low Vt and at a mean off current of 100nA/um. In fact, this 2.2 GHz part should be at least 10x lower. So the 17A number just doesn't add up for a 2.2GHz part based on device off current alone. If it did, think what the current would reach at at near 3GHz?? By the way, they include a schmoo plot for P4 operation which indicates they don't reach 3 GHZ at 1.4V and probably don't reach 3GHz in any meaningful quantity even at 1.5V. The paper also indicates they had to improve the oxide reliability to even get to 1.4V operation but now they have actually released the technology at 1.5V. I can see them tweaking their 10 yr reliability model every time they get an additional stress readout. They probably have maybe 3 years worth of stress readings by now. If it continues to look better and better we may see 1.6v before the end of this technology. That's a 10.7megaV/cm field. Astronomical. This competition is pushing Intel right to the wall with their technology. I can't wait to see when they get down to near L gate = 60NM. That's when process control will be really critical and there is no where to hide. Having all 4 devices operate in spec. and in accordance with the model at minimum channel length is very difficult. It is very easy for all hell to break loose at minimum channel length. I continually get the feeling that somebody is going to go over the cliff and start shipping some garbage parts. The question is who?? THE WATSONYOUTH

Report TOU Violation

Share This Post

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next