Combjelly, Yes, I expected that to be the case, but can you quantify that?
Bill
Each extra layer adds an additional trip around the Fab. Since AMD seems to be using a Moto's Dual Damascene Cu Process, each additional layer would most likely require (NOT Necessarily in this specific order), the addition of an Insulating Dielectric, an Litho Pattern application for the Trench, an Etch step to cut the Trench, a Litho Pattern application for the Interconect Via's, an Etch step to cut the Vias in the dielectric, the insertion of the Via Plugs, the introduction of the copper metal, and a planerization. This does not include the additional Defect Metrology, and Critical Dimension Analytical steps. My WAG would be somewhere in the neighborhood of an additional 15-20 operations per layer, or approx 45-60 additional process steps for the 3 additional Metal Layers. Each additional step has the potential for additional defect introduction.
Semi |
