Advanced Micro Devices - Moderated (AMD) Message Board

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD)

AMD 209.47

+0.9%

3:36 PM EST

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next

To: semiconeng who wrote (73482)	3/5/2002 5:19:02 PM
From: TGPTNDR	Read Replies (1) of 275872

Semiconeng, Re: <each additional layer would most likely require (NOT Necessarily in this specific order), the addition of an Insulating Dielectric, an Litho Pattern application for the Trench, an Etch step to cut the Trench, a Litho Pattern application for the Interconect Via's, an Etch step to cut the Vias in the dielectric, the insertion of the Via Plugs, the introduction of the copper metal, and a planerization. This does not include the additional Defect Metrology, and Critical Dimension Analytical steps. My WAG would be somewhere in the neighborhood of an additional 15-20 operations per layer, or approx 45-60 additional process steps for the 3 additional Metal Layers. Each additional step has the potential for additional defect introduction.> Interesting. How many weeks would you expect these * EXTRA * steps to take? tgptndr

Report TOU Violation

Share This Post

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next