tgptndr,
"Incidentaly, we have, at present time, as I said, the Holy Grail has been obtained. We have the Hammer. It's a top to bottom architecture. It's a device of 100M transistors. 100M transistors, Silicon on insulator,Copper interconnect, 130NM feature sizes, and we've got working silicon, we're running them in platforms at Redmond as we speak. Hammer is real, and so is AMD.
I don't know what's going on regarding the 100M transistors. That's a lot of transistors. I wonder if this could be some future dual core Sledgehammer. I highly doubt it will be Clawhammer.
This is what I found on Anand's site:
the Northwood core now features a 512KB L2 cache instead of the original 256KB cache. The addition of the extra cache raises the transistor count on the Pentium 4 to 55 million, up from the 42 million of the Willamette core.
anandtech.com
The Athlon (Thunderbird) core had 37 million transistors of various types, but it was AMD's first shot at an Athlon core with an on-die L2 cache. The Athlon 4 takes the same Thunderbird core and further optimizes the core by using more optimized transistors for various portions of the core. When you are dealing with the 37.5 million transistors that make up the Athlon 4, such optimizations can result in quite a bit of power savings.
anandtech.com |
