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Technology Stocks : Advanced Micro Devices - Moderated (AMD)

AMD 213.62

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3:59 PM EST

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To: Joe NYC who wrote (73577)	3/5/2002 10:38:19 PM
From: ptanner	Read Replies (1) of 275872

Joe, re: 100M transistors Some playing with numbers: Palomino = 37.5M Claw = 40M (for processor core and 256KB L2) - AMD has said x86-64 added 5% Northwood - P4 = 13M for additional 256K L2 (1) Then 100M for Hammer (presumably) could be about 2 x 40M (dual core w/256K each) plus 512K L2 for a total of 1MB L2 = 106M transistors. Fairly close but JS usually rounds up. <g> -or- (2) However, it isn't certain that dual core will be provided initially so assuming all L2 then this would be about (100-40)/13 +256K = +/- 1.4MB of L2 (I realize this is an odd value) and some transistors for dual DDR and 3HT. WAG 2 = single or dual core plus large or larger L2. Moving the memory controller and multiple HT link may require transistors not included in AMD's "5% larger" value. Someone else care to try? EDIT: I really must read all the messages before posting. <g> I like Petz's estimate of 1MB L2 single core but feel the 100M is for Sledgehammer rather than Clawhammer. I don't think 100M transistors will fit into the 104MM^2 die noted for Clawhammer (only 30% more area than Thrbred on same process). -PT

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