Re: It's a device of 100M transistors.
What may have been lost in a lot of recent analyses is that AMD evidently intends to actually use the 9 layers that their new process is capable of.
Consider the problem of routing 32 and 64 bit data paths between 10's of millions of transistors located in a rectangle. The "wires" are printed using a process analogous to photography, so wires cannot cross - they either connect to each other, or must be routed around each other to get to their destination devices. MPU printed circuits can, of course, cross each other if they are on different layers. Today, mainstream CPUs are 6 layer devices. A couple of layers for power and ground, a couple of layers for semiconductors like transistors, resistors, and capacitors, and 2 or 3 layers to route all the interconnections.
The convoluted routings necessary in P4 forced Intel to build repeaters into the a number of the circuits on the chip, so that it takes several clock cycles for some data to just move from one device on the chip to another. This is one of the reasons P4's pipeline is so long - some cycles are used to just move data along the twists and turns of the routes required to fit all those paths into 2 or 3 layers. When routing is too long, it can slow down the speed the chip is capable of operating at - in the past, "speedpath work" has enabled a doubling of the speed of some chips.
If AMD is using all 9 layers its process is capable of for the hammers, they could have 5 or 6 layers available to route datapaths. The additional freedom this gives the layout tools must be substantial. Critical speed paths will most often be fairly close to straight lines, instead of being forced to route around other busses.
50% more layers will probably be 100% harder to FAB, likely reducing yields - but are just as likely to result in devices 100% faster.
Intel's 6 layer process may have passed some point of diminishing returns as they increase the transistor budget. It's great that they have all those transistors available on their .13 and .09 processes, but given the number of interconnections necessary to keep 100 million transistors working together, it may be that Intel's CPU performance is approaching a wall that will exist until they add more layers to their process.
Does anyone know when Intel is scheduled to move to a 9 layer process?
They may not be competitive until they do... |
