Hi all; <font color=red>Intel says no more RDRAM development effort:
All Quiet On The Memory Front?
LostCircuits, March 4, 2002
Where last year's memory roadmap was still a triumph for Rambus with the perspective that they would take over the world, in retrospect, it turns out that it was their swansong instead. Unfettered of non-participation clauses regarding JEDEC discussions of DDR technology, Intel has left the Advanced DRAM Technology (ADT) consortium comprising such names as Micron, Infineon, Samsung and Hynix, other splinter groups are falling apart as well and everything is concentrating on JEDEC again, to the overt pride and joy of JEDEC chairman Desi Rhoden. Coincidentally, AMI-II is the only surviving competing organization, chaired by the very same venerable Desi Rhoden who is now presiding over the entire memory industry like the grand puppet master. With all outside enemies out of the way, JEDEC is under full sail and announced the completion of the PC2700 DDR specs during the roadmap session.
Intel's own roadmap presented by Abid Ahmad and backed by Samsung's Jon Kang showed a total of four different technologies supported at least until the end of 2004, that is if we can trust roadmap: SDRAM for the entry level, Rambus for the high performance desktop, DDR, and DDRII as an evolutionary process under development. The presentation focused entirely on DDR technology since "there is no more developmental effort at Intel for the other two technologies". [Bilow: BWAHAHAHAHAHAHA!!! LOL!!! BWAHAHAHAHAHAHA!!! Wait till this news hits Wall Street. It's going to drop your stock price in half.]
Highlights of the presentation were the technical specs of DDR II featuring On Die Termination (ODT) as well as cutting the page sizes in half at the same density and configuration during the transition from DDR to DDR II. What this means is that with the current technology and DDR design specs, a 512 Mbit die uses a page size of 8k bits or 1k column addresses. Higher densities will need to migrate to 2k column addresses which is relatively easy to implement since the additional address line (A12) is already present and can be mapped to the column decoder. Large page sizes, however cause some performance hits (depending on which chipset vendor you talk to, there are obviously some differences in opinion between AMD and Intel).
For increasing densities to 1 Gbit and beyond, the DDRII roadmap presented at IDF shows a reduction of page size or Column Addresses compensated by an increase in Row Addresses that, if I am not mistaken will require additional address lines and make DDR II not backwards compatible with the current DDR standards, at least above a certain density. It is clear that the higher density chips are intitially targeted towards the server market and the current generation of desktop chipset will not support them, including Intel's own desktop chipsets. What it will come down to is a repetition of the BX scenario where the chipset will only see half the density of the module, at least if the projected technology will pass as JEDEC standard. Who is going to bite the dust? Most likely, it is AMD with their integrated memory controller as part of the CPU since where others respin their chipset, AMD will have to revamp their CPUs and possibly add pins to accomodate the additional address lines.
Another novel development concerns the burst length of DDR II which was originally proposed as limited to 4 quad words to allow faster turnaround times without killing an ongoing burst. AMD has been pushing for a BL=8 in the past, albeit with relatively little impact on the specifications. With Intel back on the JEDEC stage, BL=8 suddenly has smooth sailing and has become one of the Intel accomplishments.
Further in the future that is towards the implementation of DDR III we will see the transition from four to eight internal banks, a feast for those who thrive on bank interleaving. Instead of the DDR II prefetch of 2 bits/pin DDR III will further double the prefetching to 4 bits. This appears a dire necessity to mask some of the extremely high latencies anticipated for even the higher speed grades of DDR II (we are talking 5:5:5 here), otherwise even streaming applications will suffer. At the same time, even with the higher DDR speed grades, tRAC (the initial access latency until first word out) will be no better than anything we have now.
The Samsung Presentation was complemented by Hidemori Inukai (Inukai-San), Board Director and VP at Elpida (former NEC and Hitachi) who completely abandoned Rambus technology in their roadmap.
Where does this leave Rambus? RDRAM 4i has completely disappeared from the PC market but will still be used in gaming consoles as a reduced cost solution. On the other hand, Yellowstone with its octal data rate (ODR) may have a comeback once the technology is mature enough to hit the mainstream market. [Bilow: i.e. 6 months after never.]
...
lostcircuits.com
Also see:
lostcircuits.com
See? I told you guys that this was in store for you. You were doomed as of late 1999 when the Camino destroyed Intel's attempt to get RDRAM into the mainstream PC market. From there, it was obvious that RDRAM would never become the mainstream memory, and that it would therefore never get cheap. That meant that Intel had to drop RDRAM from their entire line because RDRAM is lousy even as an obscure niche memory.
Now you're going to find out (the hard way) what "dead, dead, dead" means with respect to memory technologies.
-- Carl
P.S. Thanks to Rambus moron otterrivervalley on the TMF thread for the link:
boards.fool.com |
