Ali, Re: "I can imagine that. With 300++ mm die size and
140M transistors, the yield must be 1-2 dies per
wafer in a good sunny day"
Good for your imagination. But let's stick to facts, shall we?
icknowledge.com
Let's take a worst case scenario of 400mm^2 die (20mm*20mm) with .5 defects per cm^2. The calculator says 9 die per wafer. Experts on this thread before, however, say that .5 defects per cm^2 represents horrible yield.
Let's take the same size die, and decrease defects to .3 per cm^2. Die per wafer jumps to 17 good die per wafer. If we use a slightly smaller die of 324mm^2 (18mm*18mm, since large cache Xeons are likely closer to this size, rather than the former), we get 31 good die per wafer.
Finally, Intel is moving towards 300mm wafers, and the first of these are already in production. On 300mm wafers, good 324mm^2 die at a defect rate of .3 per cm^2 comes out to 73 good die per wafer.
Wafer costs, according to this link:
icknowledge.com
Are as low as $1480 for a .18u wafer, $1900 for .13u 200mm wafers, and $2900 for 300mm wafers, and since these are high ASP parts ($1000-$3000), you can be sure that Intel is making healthy margins on them.
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