Maui, Re: "BTW, I find it impossible to believe that AMD got 3 additional layers on their .09 process - somebody must be counting poly as a routing layer"
From what I heard, it was not AMD's .09u process, but rather their .13u process that is said to have 3 additional metal layers over their previous process (9 vs 6). If what you say is true, then that would give them an enormous advantage. On the other hand, I don't think it's a good idea to trivialize the costs with respect to the benefits. If more layers were as good as you say and if costs were as insignificant as you say, then everybody would be making extra interconnect layers their goal. As it is, the number of metal layers is usually lost among buzz words like gate widths, SOI, and low-k dielectrics. If extra layers were as good as you say, wouldn't you expect more bragging from AMD that they were able to get 9, while the competition is still using 6?
wbmw |
