>Here is something from the interview:
The Hammer, which is an eighth-generation processor, is 103 square mm, versus our seventh generation, which is 80 square mm. [There are] 67 million transistors in the Hammer—67 million transistors in 130-nanometer technology. It’s extraordinary.
This would also seem to confirm that Clawhammer will have 512KB L2 cache. Palomino has 37.5 million transistors with 256KB L2 cache, while Morgan has 25.2 million transistors with 64KB L2 cache. This would imply that 768KB of L2 cache would require at least 49.2 million transistors, even more with the greater number of tag bits that would be needed to accommodate Hammer's larger address space. With Clawhammer at 67 million transistors, versus 100 million for Sledgehammer, this would leave only 33 million transistors to accommodate the difference between Clawhammer's L2 cache and Sledgehammer's 1MB L2 cache, plus other differences, such as Sledgehammer's 128-bit memory controller versus Clawhammer's 64-bit memory controller.
With Clawhammer having 512KB of 16-way set associative L2 cache versus Prescott having 1MB of 8-way set associative L2 cache, it should be a pretty good matchup with regards to cache hit rate. Of course, we have even less indication that Clawhammer will have 16-way associativity and Prescott just 8-way associativity than we do that Clawhammer will have 512KB L2 cache and Prescott 1MB L2 cache. |
