"they now seem to make the most mileage out of that design lead by using a die size that maximizes revenue per wafer."
I think AMD is making a big strategic mistake by taking
a low-profile small-size path, with all this short-sighted
"revenue per wafer". They will lose in the long run.
Why?
1. In the PC business, performance sells, and will be.
Either MHz-based, which is easy to communicate to
buying public, or true performance, which must have
a clear undisputed lead.
2. As core frequencies continue to rise, the gap between
memory and processor will continue to widen, and
off-chip traffic will eventually dominate on current
platforms.
3. Effectiveness of x86 instruction set architecture (ISA)
seems to reach its limit - no matter what the implementation
is, inner performance is about the same.
4. To get more performance, the off-chip traffic must be
reduced, which means better caches, which means bigger
on-chip caches.
5. Bigger cache requires bigger die. Therefore, strategically,
the 300mm fabbing and big-die big-cache chips will
have increasing advantage, and will be more and more
economical as die shrinks.
6. Smaller-die theory will break: the die cannot be made
smaller than certain size, I guess about 80-100mm2, because
of pad/bump limitations, and current density/power dissipation limits. The smaller die will not scale down
as well as bigger die.
7. That's it. I don't know what AMD is thinking,
but the published tactics of "smaller die" is poised
to fail again, IMHO.
Sorry.
- Ali |
