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Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 221.05+1.4%3:59 PM EST
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To: Ali Chen who wrote (75626)3/26/2002 2:13:16 PM
From: combjellyRead Replies (2) of 275872
 
"They will lose in the long run."

I guess it depends on what you think the long run is. AMD needs a small die until it can get access to 300mm wafers, so basically through 2005. Now that encompasses 130, 90 and possibly 65nm. The problem with the x86 instruction set that you mention is the inability to extract a whole lot of parallelism out of the code. There are several reasons for that, a big one is the restricted number of registers that can be general purpose. Now x86-64 addresses this problem in 16 bit mode and it implements SSE-2, both of which will enable a bit more parallelism to be extracted. It also has addressed the problem of going off chip to an extent by hacking away at latency. In addition, it has reduced the number of cycles to the L2 cache to 8 from around 20 or so of the Athlon. All of this helps. But what about the future?

Well, at 90nm a SledgeHammer with 1Meg of L2 should be down to less than 100mm^2, maybe less than 90. It would also likely have DDRII for memory, keeping it's gains on latency reduction while increasing bandwidth. The move to 65nm would likely see a doubling of L2 cache again, while keeping the die size in the same range. Sure, Intel will likely have a larger L2 cache, but that is counter-balanced because they won't have the latency reduction unless they bring in an on chip memory controller. Which would complicate their SMP model enormously...
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