Ali Re...1. In the PC business, performance sells, and will be.
Either MHz-based, which is easy to communicate to
buying public, or true performance, which must have
a clear undisputed lead.<<<<<<<
While that may have been true several yrs ago; what percentage of people need a 2 ghz computer, and one of the fastest growing segments is the low end computer; such that the low end now comprise 30% of the market, and if you throw in notebooks as a low end, but not low price, the percentage of computers sold with a performance drop of better than 20% goes up dramatically. Secondly, the Hammer, with a 20-25 % improvement in IPC over Tbird will have a 40% IPC advantage over P4, which should be enough to get that clear undisputed lead in IPC.
3. Effectiveness of x86 instruction set architecture (ISA)
seems to reach its limit - no matter what the implementation
is, inner performance is about the same.<<<<<
I assume you are talking about IPC here; but doesn't the 20-25% IPC improvement in Hammer disprove that statement.
<<<4. To get more performance, the off-chip traffic must be
reduced, which means better caches, which means bigger
on-chip caches<<<<<<<
Wouldn't the cpu designers follow big iron in designing more parallelism in, and 2 cores as well as bigger caches,
<<Bigger cache requires bigger die. Therefore, strategically,
the 300mm fabbing and big-die big-cache chips will
have increasing advantage, and will be more and more
economical as die shrinks.<<<<<
From what I read about the big die theory, floating around here, about a month ago, The big die theory had less to do with better performance and efficiency than starving Intels competitors of resources (big fabs cost a lot of money) and supposed process superiority. (Only Intel has the ability to make big die chips) If you have a efficient design, and it still requires a big die, then you would be right. If you have a P4, which at almost twice the size of Tbird, still has a hard time keeping up performance wise,Tbird should win in the marketplace, because it can be produced cheaper and has better price/performance.
Smaller-die theory will break: the die cannot be made
smaller than certain size, I guess about 80-100mm2, because
of pad/bump limitations, and current density/power dissipation limits. The smaller die will not scale down<<<<<<
AMD is certainly adding cache etc. as Hammer will be over 100 mm2. I think AMD small die theory, isn't so much about die size as much as about efficiency; getting maximun use of the die size you need, rather than Intels, "Let build it big because we have a process lead."
<<. That's it. I don't know what AMD is thinking,<<<<<<
AMD could be thinking that when computers become commoditsized, the smaller, more efficient, better price/performance cpu will win a majority of customers. |
