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Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 217.91+0.9%Dec 5 9:30 AM EST
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To: Ali Chen who wrote (75688)3/27/2002 12:39:25 PM
From: pgerassiRead Replies (1) of 275872
 
Dear Ali:

Current DDRDRAM has a latency of 5 cycles 1 for command, 2 for RAS and 2 for CAS. It transfers a cache line of 64 bytes in 8 data xfers or 4 cycles. Thus latency is larger than bandwidth and that is when the memory is directly connected. Add a cycle for FSB arbitration and a cycle for NB switching and syncronization and you have 7 cycles of latency and 4 cycles of data transfer. Thus a cache line fill takes 11 cycles where bandwidth states it takes only 4 cycles to actually move the data.

So the ratio is not 1/3 but more like 50 cycles for CPU per cache line fill, 112 cycles for latency and 64 cycles for bandwidth. Bandwidth only is 64/226 or 28%. Latency is 112/226 or about 50%. Cutting latency in half increases performance by 56/170 or 33%. Doubling bandwidth only raises performance by 32/194 or 17%. Reducing latency has a higher beta to performance. Going to a 133MHZ QDR FSB for P4 reduces latency by 5 to 10 cycles and this has the higher effect than the bandwidth improvement.

As to the 75ns RAMBUS latency of on die controller, most of that is inherent to RAMBUS and probably assumes the fastest RIMMs with few memory dies. 54ns is the inherent amount for PC2700 CAS2 and that is whether 1 single sided DIMM or 2 double sided DIMMs are used.

Pete
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