>The bottom line is that AMD has lost the performance crown. The decision not to increase L2 is going to cost AMD 100s of millions of dollars this year, and will result in AMD running half empty fab.
This insistance of small die size is a disaster in the making. It erased all the strengths of Athlon processor performance-wise. The decent ASPs that AMD was able to charge will evaporate withing 2 months (I know I made this clain in January, and I was wrong, but this time it is for real).
AMD could have had Tbred with die size of approx 100mm^2 keeping up with P4 performance-wise for the rest of the year, with decent ASPs. Instead, Tbred will have die size of 80mm^2, but AMD will face a debacle in ASPs, market share (unit and revenue).<
I agree here, to a certain extent. I don't think that TBred will clock high enough for the limited amount of L2 cache to matter, but Barton should probably have 512KB L2 cache. The only way that I see for AMD's decision to cripple Barton with only 256KB L2 cache is if Clawhammer really does ship in volume in October.
If AMD can make the transition to Clawhammer as rapidly as they made the transition from K6 to K6-2, repositioning Barton to occupy the same market segment as Intel's 130nm P-III Celeron did in Q4 of last year, while flooding the Asian markets with Morgans out of Fab25 and Appaloosa in a manner similar to what Intel did with low end Celerons in Q4 of last year, the decision to limit Barton to 256KB L2 cache could prove to be an excellent one. But these are big ifs.
>AMD has basically traded ability to produce and sell 8 million CPUs from Dresden (at decent ASPs) for ability to produce 10 million CPUs, but sell only 5 million at lousy ASPs.<
>Going forward, the decision to cripple Hammer with single memory channel, and not including a forward looking size of L2, is going to make Hammer much less significant than it could have been. Again, the reason is to keep the die size down (in case demand is high, but small die and penalties that come with it will decrease demand).<
Once again, I more or less agree. AMD needs to produce a "crippled" variant of the 90nm Sledgehammer for the desktop. Such a processor might have the same number of HTT links and DP capability like the DP Clawhammer, but be sold into the desktop market at the same peak selling price as Prescott. The 90nm Clawhammer would then need to be reduced to just 256KB L2 cache and marketed against P4 Celeron, perhaps being produced using bulk silicon for economy. But, even for this to work, AMD's transition to 90nm would have to take place within four month of Intel's. |
