WATSONYOUTH - <<<<So...what is this PFET instability that gets so out of hand with a .05V increase in Vdd??? >>>>
Maybe this is what he was talking about. Looks like IBM is concerned. Remember IBM?
Reliability problems scale up as CMOS scales down
By David Lammers, EE Times
Apr 12, 2002 (2:07 PM)
URL: eetimes.com
DALLAS — Reliability experts are waving red flags about a little understood problem — negative bias temperature instability — that can cause significant delays to CMOS circuits.
The delays increase over time as chips operate at high ambient temperatures or during the product burn-in cycle. Many companies are scrambling to alter their process technologies to suppress NBTI, and they're warning both digital and analog engineers about the design implications.
At the International Reliability Physics Symposium here this past week, IBM Corp.'s Giuseppe La Rosa said the issue is drawing wide attention. "Everybody is screaming, and this is a sign that this is a critical issue," he said.
Unlike the well-understood problem of hot carriers in NMOS field-effect transistors, NBTI is "very difficult to design around," said LaRosa, senior scientist at IBM's research center in East Fishkill, N.Y.
Over a period of months or years, depending on the chip's operating conditions, NBTI causes the threshold voltage in PMOS FETs to shift by as much as 50 to 100 millivolts, making it tougher to turn on the device, La Rosa said. That has particularly serious implications for analog circuit designers, who need to closely match the Vth in both the NMOS and PMOS FETs.
"For analog circuit designers, even a 10-mV or 20-mV mismatch is a big problem," said La Rosa, who presented an NBTI tutorial at the symposium.
Prasad Chaparala, a senior device reliability engineer at National Semiconductor Corp., said negative bias temperature instability is caused when holes become trapped in the interface of the SiO2 gate insulator and the silicon substrate.
"At National, because analog and mixed-signal products are a big part of our business, we have had a major program to educate our designers about NBTI, to get the designers to provide enough tolerance in their circuits. If they know the Vth can shift 50 mV, then they might be able to compensate. But the designer has to be able to tolerate the drift in the threshold voltage. To some extent NBTI depends on the application, though we think it applies to virtually all CMOS devices at cutting-edge rules," said Chaparala.
The problem has become evident at 0.13-micron as companies build much-thinner gate oxides and introduce nitrides in the SiO2 to prevent boron penetration into the gate. Another cause may be plasma-induced damage during interconnect creation, driving hydrogen atoms into the Si-SiO2 interface.
NBTI worsens at high temperatures, such as the 150°C heat typical of burn-in, or the 100°C ambient temperatures a microprocessor reaches in normal operations. The heat creates stresses that shift the threshold voltage over time.
Degraded performance
Also, NBTI looms larger as voltages are scaled. In a paper at IRPS, Vijay Reddy, a reliability engineer at Texas Instruments Inc., showed that the performance of a nominal 1.5-volt ring oscillator test circuit created with 0.13-micron design rules was degraded by NBTI under stress conditions.
Depending on how much stress was applied to the test circuit, performance worsened by as much as 12 percent. But Reddy said that in real-world circuits, performance degradation is likely to vary widely according to the circuit design, and he declined to estimate how large an impact NBTI might have in actual products.
NBTI is important to TI, which emphasizes reliability, because NBTI is particularly troublesome for low-voltage chips used in battery-powered systems.
Because the shift in the threshold voltage reduces the amount of transistor-gate overdrive — i.e., the difference between the operating voltage and the threshold voltage — "the circuit impact of NBTI is expected to worsen as Vdd scaling continues," Reddy said in his presentation.
Some companies, IBM and TI among them, say they have altered their process technology to partially solve the problem, but they are not making those changes public.
La Rosa said companies routinely use BF2 — a boron-fluorine gas — during processing. Too much fluorine can increase boron penetration. The trick is to "play with the implants" and induce the fluorine to bond with silicon atoms at the Si-SiO2 interface, replacing silicon-hydrogen bonds with silicon-fluorine bonds.
Joe McPherson, a TI senior fellow and reliability manager, said TI scientists believe "hydrogen is the fundamental issue with NBTI. Companies have started using oxynitride as the gate insulator in order to minimize boron diffusion. At the Si-SiO2 interface, you need hydrogen to tie up the dangling bonds, but too much causes a problem."
Not a showstopper
NBTI is "very voltage-dependent, and it absolutely is an issue any time you need to have closely matched [PMOS and NMOS] transistors," he said. Calling it "more of an issue for analog," McPherson said NBTI is "by no means a showstopper."
La Rosa said circuit designers traditionally have worried more about hot carrier effects in the NMOS devices, and have allocated a large part of their reliability budget to the NMOS devices. But with NBTI becoming a bigger problem, designers now must portion out the same reliability budget equally over the NMOS and PMOS devices.
Chaparala said EDA companies need to work NBTI into their models and tools, adapting for possible shifts in performance. The Joint Electron Devices Engineering Council (Jedec) is trying to standardize a test methodology that would help identify just how much NBTI degrades performance. Eric Snyder, a vice president at Sandia Technologies Corp. (Albuquerque, N.M.), heads a Jedec effort to develop those test modules.
One potential long-term implication of NBTI: Some companies may no longer perform burn-in testing, today's dominant way to ensure reliability. Burn-in also poses a problem because "the parts already run so hot through self-heating that we face thermal runaway" during burn-in, Snyder said.
In addition, as voltages scale down to 1 V, burn-in requires "an excruciating amount of time," he said.
Over time, heat from burn-in and normal operation slows the PFETs in CMOS. Reliability engineers, traditionally concerned about hot-carrier effects in NFETs, now must confront heat in surface-channel PFETs.
Copyright 2002 © CMP Media, LLC |
