Hi all; Memory expert chosen for German trial publishes flyer with chart showing SDRAM to be superior to RDRAM. BWAHAHAHAHAHA!!! LOL!!! BWAHAHAHAHAHAHA!!!
Lothar Thiele was chosen as the independent expert to evaluate Rambus' patents:
Rambus' Latest Legal Developments
Bill Tell, Hager Technology Research, 11/30/01, 12/13/01
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Moving forward: in the near-term, we await the results from Germany of the independent expert’s evaluation of the one patent at suit in the Rambus vs. Infineon case there. The expert, Dr. Thiele a university professor from Zurich, is expected to issue his opinion sometime towards the end of Q1 2002. This case is equally, if not more important to Rambus than the U.S. one, as most of Infineon’s manufacturing takes place there. And with all the lingering doubts about the legitimacy of the U.S. Markman ruling, which severely narrowed the interpretation of Rambus’ patents in the U.S., another third party confirmation of how sound their patents are in Europe is vital in gauging the company’s legal strength abroad.
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siliconinvestor.com
Okay. So what does Lother Thiele think about RDRAM? Here's the answer: "DDR rules! Rambus drools!" BWAHAHAHAHAHA!!! LOL!!! BWAHAHAHAHAHA!!!
Look at the chart "normalized execution times" on page 2, upper right corner of the following (pdf) flyer:
IP3 Internet Protocol Packet Processor
Institut fur Technische Informatik und Kommunikationsnetze, Zurich
IP3 covers the design and implementation of a compact IP packet processor architecture. This project is a cooperation between TIK and Inalp Networks Inc., Niederwangen.
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Prof. Lothar Thiele
Mathias Gries
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tik.ee.ethz.ch
BWAHAHAHAHAHA!!! LOL!!! BWAHAHAHAHAHAHA!!! Call an ambulance, I'm laughing so hard that I can't breathe!
If looking at the chart on the above isn't enough to convince you that the guy doesn't like RDRAM, then maybe you should read the paper that his graduate student (Mathias Gries, listed as an author of the flyer linked in above) wrote associated with the research for the above flyer:
Algorithm-Architecture Trade-offs in Network Processor Design
Mathias Gries, PhD thesis, ETH Zurich, Switzerland, ETH Diss No 14191, May 2001
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SDRAMs are preferred over RDRAMs since accesses of parameters and variables are rather small so that an RDRAM cannot take advantage of its superior bus bandwidth. [page 76/86]
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DRAM throughput vs latency properties: The comparison of SDRAMs with RDRAMs has shown that the performance advantage of RDRAMs is rather caused by improved bus bandwidth than by any other architectural property. The use of a high throughput interface could therefore be beneficial. The access granularity of an RDRAM however is relatively coarse compared with an SDRAM. Forthcoming double data rate (DDR) SDRAMs could therefore be a more flexible solution if different or finer access resolutions were required. [page 154/164]
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The exploration of operating modes of a memory controller has shown that a controller indeed has a high impact on the overall performance of a memory subsystem. Taking advantage of the pipelined interface and the row-wise organization of DRAMs has less effect on the performance than making use of several internal memory banks by simple address permutations. Moreover, the performance advantage of RDRAMs compared with SDRAMs is due to the improved bus bandwidth rather than any other architectural property. It is thus feasible and pragmatic to integrate a network processor with an application-specific memory controller that supports simple operating modes and a high-bandwidth interface. [page 156/166]
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tik.ee.ethz.ch
The above paper was linked in by Bilow on December 13, 2001: #reply-16784883 . The flyer is a new link. This quarter, Rambus is going to get the ruling in the German patent case and it is not going to be good news for Rambus.
-- Carl |
