SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 258.99+2.1%12:31 PM EST
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Dan3 who wrote (77855)4/21/2002 5:15:45 PM
From: hmalyRead Replies (1) of 275872
 
Dan3 Re...And PIII, if banias keeps the same cacheline, caches twice as many locations, per K, as Athlon (4 times as many as P4). <<<<<<<<<

INteresting thought. According to Van's Intel is changing the bus to a P4 bus. Banias is essentially a Pentium III core fitted to a low-voltage 400 MHz Pentium 4 bus. Some architectural changes had to be made to the PIII core to accommodate a doubled 64-byte L2 line size.

The Level 2 cache size is 1MB. <<<<<

If Intel had to change the L2 cacheline to 64 bytes for the P4 bus, isn't it likely the cache would be set up the same as P4 and therefore will only address one half of Athlons locations? Also, Van states that Intel did that partly for thermal properties. Does addressing the cache like P4 result in a cooler cache than PIII style cache? Thanks.
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  

HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2026 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News