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Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 261.60+3.1%11:25 AM EST
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To: hmaly who wrote (77868)4/21/2002 11:52:44 PM
From: Dan3Read Replies (2) of 275872
 
Re: If Intel had to change the L2 cacheline to 64 bytes for the P4 bus, isn't it likely the cache would be set up the same as P4 and therefore will only address one half of Athlons locations?

I missed the quote about the changed cacheline. You've raised a very good point - it looks like banias will only address half the number of locations per K of cache. As far as power consumption is concerned, caches use a lot less per transistor than logic. I don't know why, but I do know that the power consumption of caches is sometimes listed separately - and it's never more than a few watts, even for large caches, so I'm a bit skeptical that increasing cacheline length will save all that much power. Maybe Scumbria will return and tell us why this is...
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